In today's electronics industry, advanced packaging techniques are being developed and continue to be developed to increase levels of integration. Semiconductor devices are formed on a semiconductor substrate, also known as a wafer, which includes a multitude of individual semiconductor devices, known as chips after they are separated from one another. After semiconductor devices are formed on a semiconductor substrate, and separated into the individual chips, the chips must be bonded to other chips and/or other components and it is logically desirable to join as many semiconductor chips as possible in a package of reduced size.
All of the bonding techniques used in chip to chip bonding involve joining opposed surfaces of the bonding materials formed on the respective chips. The bonding materials may be a metal or a metal alloy and in each case, it is a challenge to provide good contact and a strong bond between the bonding materials of the respective chips especially since the bonding surfaces are prone to oxidation after they have been formed and patterned and the presence of a surface oxide limits metal to metal diffusion such as needed to form a strong metal bond. The time delay between the deposition of the bonding material, the patterning of the bonding material and the actual bonding can be considerable and the metal surfaces can oxidize during these time delays, inhibiting the subsequent metal diffusion between bonding surfaces and degrading bonding strength and quality, adversely impacting the package's quality.
It would therefore be desirable to overcome these limitations and provide a method and structure that provides high bonding strength and eliminates the source and impact of bond degradation such as native oxides.
Wafer Level Chip Scale Packaging, WLCSP, and other hermetic packaging techniques bond chips directly together and can be used to produce finer pitch semiconductor device packages and products that do not require wires or pins but instead utilize contact pads. Direct chip to chip, also referred to as wafer to wafer bonding techniques are utilized in such advanced packaging techniques and require superior wafer bonding strength and hermeticity for package qualification. Each of these aspects requires high quality bonding surfaces to be joined together.
Previous approaches to improved bonding techniques include the development of glass frit and anodic bonding techniques to achieve hermetic packaging. These techniques have limited applicability, however, as they are not scalable for the bonding of smaller devices and are not appropriate for the bonding of semiconductor chips utilizing CMOS technology and structure or MEMS, micro-electromechanical structures.
Bonding techniques that provide high bonding strength and hermeticity in wafer to wafer bonding, are needed.